U.S. Pat. No. 8,384,440 B2, issued Feb. 26, 2013, provides a method of capturing time-stamping of input signals with very high resolution without requiring high frequency sampling. This patent, which shares inventorship with the present patent application and which is hereby incorporated by reference, uses a capture delay line to time stamp an input edge of signal as a fraction of the sampling frequency. The capture delay line receives the input signal at a first end and receives a version of the input signal that is synchronized to a clock signal at a second end that is opposite the first end. These two signals propagate toward one another through a sequence of capture delay elements. When the capture delay line is calibrated to the sampling frequency, the point at which the two signals cross each other within the sequence of capture elements indicates the time of signal transition at a resolution greater than possible via the sampling frequency clock alone. However, the use of this capture delay line is limited in the frequencies at which the circuit can be used. Additionally, calibration of the capture delay line requires both intensive calculations and that the delay line be offline for the duration of the calibration. Improvements to the existing circuit are desirable.